This invention concerns the measurement of lateral diffusion in the manufacture of small semiconductor structures such as those used in the source and drain regions of complimentary-metal-oxide-semiconductor (CMOS) transistors in integrated circuits.
Some of the prior art methods for measuring lateral diffusion (identified by how far the junction moves laterally during anneal) and abruptness (which is defined by the slope of the diffused profile) include electrical probing of transistors, capacitance atomic force microscopy (C-AFM), and inference from vertical secondary ion mass spectroscopy (SIMS) profiles.
Inference of lateral diffusion and abruptness is possible from electrical probing of transistors. This procedure requires contact to a full transistor structure. Consequently, electrical probing is impractical at the point in the process when the doped layers are being formed and the transistor is still incomplete. The time between the source/drain (S/D) process steps and the first opportunity to probe can be days or weeks, greatly reducing the ability to implement real-time process control.
Probe methods such as capacitance atomic force microscopy (C-AFM) require sectioning of the transistor and various intermediate preparation steps. Even when this is complete, probing requires several hours, and the resolution is typically too poor to provide an accurate measure of diffusion for purposes of process control.
A current extraction method of laterally doping profiles requires a large series of process splits (spacer/extension variation) to create the devices. In addition, the method depends on Cov (gate-to-extension overlap capacitance) and Leff (gate-to-extension effective length) measurements which are problematic due to a high variance in these measurements as CMOS devices are made smaller.
It would be desirable to have a method for determining lateral diffusion profiles in CMOS devices without the need for process splits or Cov and Leff measurements.